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Makefiler, adskillelse af kildefiler og objektkode



Hej

Hvad skal jeg gøre for at få make til at fungere rigtigt når jeg vil adskille kildekode og objektkode.

Jeg har tidligere anvendt make/configure udfra en model hvor kilde og bjektkode lå sammen. En makefile.in så da typisk sådan ud (forenklet):

------------------------

.SUFFIXES: .cpp
SRC = $(wildcard *.cpp)
OBJS = $(SRC:.cpp=.o)
INCLUDEPATH = -I./some/path

.cpp.o: $(OBJS)
	$(CXX) @CXXFLAGS@ -c $< $(INCLUDEPATH)

all: $(OBJS)

-------------------------

Hvis jeg ændrer
SRC = $(wildcard *.cpp)
til
SRC = $(wildcard @srcdir@/*.cpp)

kan jeg ganske vist kalde make fra et andet dir, og få objektkoden til at ligge her, men make vil (naturligvis) kompilere det hele forfra hver gang.

Hvad er standard løsningen?

NB: Jeg er vil foretrække at undgå automake...

mvh Kristian

 
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